1. Field of the Invention
The present invention relates to methods and apparatuses for inspection of wafers, in particular for detection of cracks formed in wafers during dicing. The present invention also relates to methods for inspection of cracks and defects formed in semiconductor devices during manufacturing.
This application claims priority on Japanese Patent Application No. 2006-220898 and Japanese Patent Application No. 2006-277490, the contents of which are incorporated herein by reference.
2. Description of the Related Art
Due to recent developments of electronic devices such as portable terminals in terms of multiple functions and highly sophisticated functions, it is strongly demanded that semiconductor chips for use in electronic devices be downsized and reduced in thickness and be capable of performing high-speed processing. To meet such demands, semiconductor chips encapsulated in housings such as WL-CSP (i.e., Wafer Level Chip Size Package) have attracted attention of engineers and manufacturers. A typical example of the WL-CSP, i.e., a WL-CSP 1, will be described with reference to FIGS. 10 and 11. An IC 3, a pad electrode 4, a re-wire 5 electrically connected to the IC 3 via the pad electrode 4, and an electrode terminal (e.g., a metal post) 6 are formed on a surface 2a of a wafer 2 having a disk-like shape composed of polycrystal silicon or monocrystal silicon. In addition, resin sealing (i.e., formation of a resin layer 7) for protecting the IC 3 from heat, light exposure, and physical impact is also performed on the surface 2a of the wafer 2. In a last stage of manufacturing, individual ICs are isolated from each other by way of dicing along dicing lines 8. Thus, it is possible to simultaneously produce a plurality of semiconductor chips 1, each of which has an isolated wafer portion (i.e., a substrate) 2 having a rectangular shape in plan view, by use of a single wafer 2 having a disk-like shape. This noticeably improves the manufacturing efficiency, and this makes it possible to realize noticeable downsizing of the semiconductor chip 1 whose size is substantially identical to the size of the IC 3 after packaging.
During the manufacturing of the semiconductor chip 1 encapsulated in the WL-CSP, or during the conventionally-known manufacturing in which a wafer having a disk-like shape is subjected to dicing in advance so as to produce semiconductor chips, cracks, which are elongated inside of the semiconductor chips 1 from the cut surfaces of the wafer 2, may occur due to cutting resistance of dicing. For this reason, individually isolated semiconductor chips (or individually isolated portions, i.e., substrates, of a wafer) are subjected to inspection to determine whether or not cracks occur, thus checking the quality of products.
Japanese Unexamined Patent Application Publication No. H06-148144 teaches an example of an inspection device, in which semiconductor chips (or individually isolated wafers) are subjected to inspection using an ultrasonic image device equipped with a water tank storing pure water and an ultrasonic probe disposed in pure water of the water tank. In this inspection device, a semiconductor chip (or an inspected subject) is partially soaked in pure water, in which the ultrasonic probe scans the lower portion of the semiconductor chip while transmitting and receiving ultrasonic waves via pure water, whereby the inside of the semiconductor is converted into a visual image based on received reflection signals. This makes it possible to perform nondestructive inspection to determine whether or not cracks occur in the inside of the semiconductor chip or wafer.
In the ultrasonic inspection using the ultrasonic image device, it is necessary to provide pure water which the semiconductor chip (or the individually isolated wafer) is partially immersed in; and it is necessary to use dry baking for removing water content adhered to it after inspection. That is, a complex and troublesome operation is necessary in the ultrasonic inspection. In addition, the ultrasonic inspection needs human power for the maintenance of the ultrasonic probe precipitated in pure water. Furthermore, due to the immersion of the semiconductor chip in pure water during inspection, the semiconductor chip suffers from secondary appearance defects such as staining due to water content adhered thereto.
In order to accurately detect cracks elongated in slanted directions it is necessary to reduce the scanning speed of the ultrasonic probe, or it is necessary to perform scanning on one spot plural times. This increases the inspection time. Since the semiconductor chip is partially immersed in pure water during inspection, it is very difficult to simultaneously perform inspection on the lower surface and side surfaces (or cut surfaces) of the individually isolated wafer. This also increases the inspection time.
Japanese Unexamined Patent Application Publication No. 2003-51518 teaches a manufacturing method of a semiconductor device, in which ICs and pad electrodes are formed on the surface of a wafer having a disk-like shape composed of polycrystal silicon or monocrystal silicon, then, an extension sheet (or a dicing tape) for use in dicing is adhered onto the backside of the wafer. In this state, a probe is used to inspect the electric characteristics of the semiconductor chips formed on the wafer so as to check the qualities of the semiconductor chips, wherein inspection results are recorded on the backside of the dicing tape at prescribed positions corresponding to the semiconductor chips. Thereafter, the wafer is subjected to cutting (or dicing) so as to isolate individual semiconductor chips, wherein the individual semiconductor chips are subjected to screening based on the inspection results when they are separated from the dicing tape.
During dicing, cracks may be formed in the backside of the semiconductor chip produced using the wafer, or the semiconductor chip may be partially defective. The aforementioned document simply teaches the inspection of electrical characteristics of semiconductor chips prior to dicing; but this is an insufficient way of inspection of semiconductor chips.
The other conventionally-known technology teaches the exterior inspection in which, after dicing, semiconductor chips are each separated from a dicing tape so as to capture backside images thereof, so that cracks and defects formed in the backsides of the semiconductor chips can be visually detected; however, this method cannot always detect fine cracks and fine defects. Before dicing, the backside of die wafer forming semiconductor chips is subjected to polishing using a grinder so that the semiconductor chips are each reduced in thickness, wherein polished marks remain on the backsides of the semiconductor chips, which make it very difficult to detect cracks by way of the exterior inspection.